\section{Experiment Results}\label{sec:experiment}
\subsection{Simulation Setup}\label{sec:setup}
The NV-Sim~\cite{memristor:Cong}, which is an extended version of CACTI tool for nonvolatile memory, is used to simulate the area, energy and performance of the memristor-based ReRAM. The ECC encoder and decoder circuits are synthesized by Synopsis Design Compiler with 45nm technology to get the delay, energy and area values. Besides, according to Cong's
work~\cite{memristor:Cong}, the design parameters of the memristor-based
ReRAM is summarized in Table~\ref{tab:para}. Table~\ref{tab:error_rate} shows the BER requirement, $p(E)$, for a single cell within different ECC schemes to satisfied the block error rate $P_{err}<10^{-9}$.

\begin{table}[!htb]
\scriptsize \centering \caption{BER requirement with
$P_{err}<10^{-9}$}\label{tab:error_rate}
\begin{tabular}{c|c|c|c|c|c}
  \hline  \hline
  N & 1 & 2 & 4 & 8 & 16\\
    \hline
\!\!\!\!SEC-DED\!&\!$8.9\!\times\!10^{-8}$\! &\!$1.8\!\times\!10^{-7}$\!&\!$3.5\!\times\!10^{-7}$\!&\!$7.1\!\times\!10^{-7}$\!&\!$14.1\!\times\!10^{-6}$\!\!\!\\
\!\!\!\! BCH\_2\!&\!$3.9\!\times\!10^{-6}$\!&\!$7.2\!\times\!10^{-6}$\!&\!$1.5\!\times\!10^{-5}$\!&\!$2.9\!\times\!10^{-5}$\!&\!$5.8\!\times\!10^{-5}$\!\!\!\\
\!\!\!\! BCH\_3\!&\!$2.5\!\times\!10^{-5}$\!&\!$5.0\!\times\!10^{-5}$\!&\!$9.9\!\times\!10^{-5}$\!&\!$1.9\!\times\!10^{-4}$\!&\!$3.9\!\times\! 10^{-4}$\!\!\! \\
\!\!\!\! BCH\_4\!&\!$8.1\!\times\!10^{-5}$\!&\!$1.6\!\times\!10^{-4}$\!&\!$3.2\!\times\!10^{-4}$\!&\!$6.4\!\times\!10^{-4}$\!&\!$1.3\!\times\!10^{-3}$\!\!\!\\
\!\!\!\! BCH\_5\!&\!$1.9\!\times\!10^{-4}$\!&\!$3.9\!\times\!10^{-4}$\!&\!$7.7\!\times\!10^{-4}$\!&\!$1.5\!\times\!10^{-3}$\!&\!$3.1\!\times\!10^{-3}$\!\!\!\\
\!\!\!\! BCH\_6\!&\!$6.0\!\times\!10^{-4}$\!&\!$1.2\!\times\!10^{-3}$\!&\!$2.4\!\times\!10^{-3}$\!&\!$4.8\!\times\!10^{-3}$\!&\!$9.6\!\times\!10^{-3}$\!\!\!\\
  \hline
\end{tabular}
\vspace{-0pt}
\end{table}


%The geometry variation of the memristor cell is generated by using the parameters of $\Delta=2nm$, $\Lambda=20nm$, and $\sigma_{thik}=\sigma_{cont}=2\%$, where $\Delta$ is the RMS amplitude and $\Lambda$ is the correlation length to generate the LER and $\sigma_{thik}$ and $\sigma_{cont}$ are the standard deviation of thickness variation and the resistance variation of the electrode contacts.
%The Monte-Carlo simulation is used to evaluate the impact of process variations on the memristor memory. The $p_E$ value is set to $10^{-4}$, which results in that the write energy increases by about 15\% for thin film memristor and by about 25\% for spintronic memristor. Also, with the desired error rate for the whole block after ECC as $10^{-12}$, we can get the minimum ECC requirement shown in Table.\ref{tab:requir}.

\begin{table}[!htb]
\scriptsize \centering \caption{Physical Parameters of Memristor-Based Memory~\cite{memristor:logarithm,memristor:Cong}.}
\label{tab:para}
\begin{tabular}{|c|c|c|}

  \hline  \hline
  Memristor Array Architecture & MOS based & Cross-Point based \\\hline
  Cell Size  & $4F^2$ & $20F^2$\\\hline
  Memory Capacity & \multicolumn{2}{|c|}{128 MB} \\\hline
  $\sigma$ & \multicolumn{2}{|c|}{0.5} \\\hline
  SET Voltage & \multicolumn{2}{|c|} {$2.0V$} \\\hline
  RESET Voltage & \multicolumn{2}{|c|} {$-2.0V$} \\\hline
  Write Latency & \multicolumn{2}{|c|} {$100ns$} \\\hline
  Low Resistance & \multicolumn{2}{|c|}{$10K\Omega$} \\\hline
  High Resistance & \multicolumn{2}{|c|}{$500K\Omega$} \\\hline
  Target Block Error Rate & \multicolumn{2}{|c|}{$p_{err}<10^{-9}$} \\\hline
  Default ECC Code & \multicolumn{2}{|c|}{SEC-DED} \\\hline
  \hline

\end{tabular}
\vspace{-5pt}
\end{table}
%
%\begin{table}[!htb]
%\scriptsize \centering  \caption{ECC requirements with different N }
%\label{tab:requir}
%\begin{tabular}{c|c|c}
%
%  \hline  \hline
%  N & subblock size & ECC \\\hline
%  1 & 512 bits & $BCH_6$ \\
%  2 & 256 bits & $BCH_5$ \\
%  4 & 128 bits & $BCH_4$ \\
%  8 &  64 bits & $BCH_4$ \\
%  16 & 32 bits & $BCH_3$ \\
%  \hline
%%
%%  % after \\: \hline or \cline{col1-col2} \cline{col3-col4} ...
%%  Thin Film Memristor& Description   & Value     \\\hline
%%  $R_{on}$      &   Low Resistance of Bottom Oxide      & $ 200K~\Omega$\\
%%  $R_{off}$     &   High Resistance of Bottom Oxide     & $1800K~\Omega$\\
%%  $h$           &   Thin Film Thickness &   $5nm$\\
%%  $W\times{L}$           &   Cross section area      &$30nm\times{30nm}$\\
%%  $V_{w}$ &   Write voltage & 2V \\
%%  $V_r$    &   Read voltage& 0.4V \\
%%  \hline\hline
%%  Spintronic Memristor& Description   & Value     \\\hline
%%  $R_{on}$      &   Low Resistance of Bottom Oxide      & $2.5K~\Omega$\\
%%  $R_{off}$     &   High Resistance of Bottom Oxide     & $7.5K~\Omega$\\
%%  $\Gamma_v$       &   Equivalent dopants mobility& $10^{-7} m^2/V\cdot{s}$\\
%%  $h$           &   Thin Film Thickness &   $5nm$\\
%%  $W\times{L}$           &   Cross section area      &$30nm\times{30nm}$\\
%%  $V_{w}$ &   Write voltage & 2V \\
%%  $V_r$    &   Read voltage& 0.4V \\
%%  \hline
%\end{tabular}
%\vspace{-8pt}
%\end{table}

\subsection{Simulation Results}
In this section, we evaluate the area, latency and energy overhead ratio
of different ECC schemes by using the following equations:
%\begin{eqnarray}
%\label{equ:model2}
\begin{align}
R_A  & =[\Delta (A_{cell} + A_{circuit}) + A_{Enc}+ A_{Dec}]/A_0\\
R_{L\_read} & =  [\Delta L\_read_{circuit} + L\_read_{Dec}]/L\_read_0 \\
R_{L\_write} & = [\Delta L\_write_{circuit} + L\_write_{Enc}/L\_write_0\\
R_{E\_read} & =  [\Delta E_{programming} + E_{Dec}]/E_0\\
R_{E\_write} & = [\Delta E_{programming} + E_{Enc}]/E_0,
\end{align}
%\end{eqnarray}
which is calculated as the ratio of overhead to original value. For
example, the $A_0$ is the base area of the memristor ReRAM without ECC,
and the $R_A$ is the ratio of the extra area to $A_0$. Note that the area
overhead, $R_A$, counts the overheads of both encoder and decoder at the
same time. However, the decoder only affects the latency and energy of
read operation whereas the encoder only affects write operation.

\subsubsection{Area Overhead of ECC Schemes}
Firstly, the area overhead ratio of 128MB cross-point memristor-based memory is shown in Table.\ref{tab:oh_area}. Compare to Table.\ref{tab:ovhd}, it is clear that the area overhead increases monotonically with the increase of cell number overhead. That is because the overhead of the encoder and decoder is much smaller compared to the area increase of the memory array. Due to the limit of the space, the area overhead of MOS based array is not listed. However, since the based line are of the MOS based array is $78.251mm^2$, which is about twice compared to the cross-point array, the area overhead for MOS based memory array is almost the half of the cross-point array.

\begin{table}[!htb] \scriptsize \centering
\caption{Area overhead ratio of 128MB cross-point memristor-based memory (Baseline
Area=42.76$mm^2$)}\label{tab:oh_area}
\begin{tabular}{c|c|c|c|c|c}
  \hline  \hline

  N & 1 & 2 & 4 & 8 & 16\\
    \hline
    SEC-DED &       0\% &	              1.51\% &	 4.11\% &	                            8.73\% &	                   16.64\% \\
    BCH\_2  &       1.55\% &	              4.15\% &	8.77\% &	                             16.67\% &	                   29.80\% \\
    BCH\_3  &        3.27\% &	              7.12\% &	14.09\% &	                  25.87\% &	                   45.64\% \\
    BCH\_4  &       5.80\% &	             10.18\% &	19.33\% &	 35.14\% &	            61.39\% \\
    BCH\_5  &       6.61\% &	    13.15\% &	24.66\% &	 44.33\% &	            77.23\% \\
    BCH\_6  &       8.24\% &	16.12\% &	29.90\% &	 53.53\% &	 93.00\% \\
%    BCH\_7  & \textbf{11.76\%} &	\textbf{20.89\%} &	\textbf{37.02\%} &	 \textbf{64.60\%} &	\textbf{110.54\%} \\
  \hline
\end{tabular}
\vspace{-8pt}
\end{table}

\subsubsection{Performance Evaluation}

The performance results are shown in Figure~\ref{fig:R_L} and Figure~\ref{fig:W_L}. Figure~\ref{fig:R_L} shows the normalized overheads of read latency. Basically the overhead of read latency for a given ECC decreases with the increase of the number of subblocks. The reason behind this trend is that the decoders can work in parallel with each others for different subblocks. Thus the decoder latency will be reduced with the decrease of subblock size. Also, the read latency increases with the error correction capabilities of ECC codes, which results from the complexity of ECC decoder circuits. Another interesting observation is that the read overhead is more serious to cross-point memory array, which is because the baseline read latency of cross-point array (1.8ns) is smaller than the MOS based array (6.5ns). However, Figure~\ref{fig:W_L} shows the write latency of the array can be improved as much as 30\% with SEC-DED ECC code and can be further reduced by applying more powerful ECC code.
\begin{figure}
\centering
   \includegraphics[width=0.5\textwidth]{./figures/R_L.pdf}\\
  \vspace{-3pt}
  \caption{Read Latency Overhead (Based Line Latency = 6.5 ns for MOS based memory and 1.8ns for cross-point memory).}\label{fig:R_L}
  \vspace{-0pt}
\end{figure}
\begin{figure}
\centering
   \includegraphics[width=0.5\textwidth]{./figures/W_L.pdf}\\
  \vspace{-0pt}
  \caption{Write Latency Improvement (Based Line Latency = 104.1 ns for MOS based memory and 200.4 ns for cross-point memory).}\label{fig:W_L}
  \vspace{-10pt}
\end{figure}

%From the simulation results, we also find that the impact on write latency is very small and for all the ECC codes, the overhead ratios for write
%latency always in the range of: $0<R_{L\_write}<0.015\%$, meaning that the overhead in the write latency is neglectable. The reason is that for the
%memristor based ReRAM, the write latency is much bigger than read latency
%and in the range of ~100ns. Besides, for the reliability issues, in the
%cross point structure, a two-step writing methodology is
%used~\cite{memristor:Cong}, which farther increase the write latency.
%Also, note that, the writing is operated with the encoding operation. The
%structure for a encoder is quite simpler than the structure of decoder.
%Finally, for a memory system, the write operation is always not as crucial as read operation to the system performance. Therefore, we conclude that
%during the design step of a memristor based ReRAM, the write latency
%overhead is not a very significant constraint.
%
%The overhead ratios for read latency are listed in Table~\ref{tab:oh_readL}.
%Clearly, the impact on the read latency is more significant than that on
%write latency. That is because the read latency is small and the BCH decoder
%is much more complex than the encoder. Another observation is that the
%overhead of read latency for a given ECC decreases with the increase of the
%number of subblocks. The rational behind this trend is that the decoders can
%work in parallel with each others for different subbolcks. Thus the decoder
%latency will be reduced with the decrease of subblock size.

%\begin{table}[!htb]
%\scriptsize \centering \caption{Read latency overhead ratio of 128MB
%ECC-memristor based memory (Baseline Read
%Latency=2.58ns)}\label{tab:oh_readL}
%\begin{tabular}{c|c|c|c|c|c}
%
%  \hline  \hline
%    N & 1 & 2 & 4 & 8 & 16\\
%    \hline
%    SEC-DED & 28.31	\% &	27.20			\% &	26.32	\% &	25.93		 \% &	26.40        \% \\
%BCH\_2  & 56.06	\% &	53.97			\% &	52.31	\% &	51.43		 \% &	51.87        \% \\
%BCH\_3  & 85.16	\% &	82.16			\% &	79.84	\% &	78.67		 \% &	\textbf{ 79.57\%} \\
%BCH\_4  & 115.19\% &		111.33	\% &	\textbf{108.30\%} &		 \textbf{106.91\%} &		\textbf{108.21\%} \\
%BCH\_5  & 146.01\% &		\textbf{141.23\%} &	\textbf{137.55\%} &		 \textbf{135.86\%} &		\textbf{137.63\%} \\
%BCH\_6  & \textbf{177.41\%} &		\textbf{171.75\%} &	\textbf{167.38\%} &		\textbf{165.43\%} &		\textbf{167.64\%} \\
%%BCH\_7  & \textbf{209.37\%} &		\textbf{202.79\%} &	\textbf{197.76\%} &		\textbf{195.56\%} &		\textbf{198.17\%} \\
%
%  \hline
%\end{tabular}
%\vspace{-15pt}
%\end{table}
%%
%\begin{table}[!htb] \scriptsize \centering \caption{Write latency overhead ratio of 128MB
%ECC-memristor based memory}\label{tab:oh_area}
%\begin{tabular}{c|c|c|c|c|c}
%
%  \hline  \hline
%    N & 1 & 2 & 4 & 8 & 16\\
%    \hline
% SEC-DED & 0.019	\% &	0.018	\% &	0.018	\% &	0.019	\% &	0.020    \% \\
%BCH\_2  & 0.037	\% &	0.036	\% &	0.036	\% &	0.037	\% &	0.039    \% \\
%BCH\_3  & 0.056	\% &	0.054	\% &	0.054	\% &	0.056	\% &	\textbf{0.060\%} \\
%BCH\_4  & 0.075	\% &	0.074	\% &	\textbf{0.073\%} &	\textbf{0.076\%} &	\textbf{0.081\%} \\
%BCH\_5  & 0.095	\% &	\textbf{0.093\%} &	\textbf{0.093\%} &	\textbf{0.096\%} &	\textbf{0.103\%} \\
%BCH\_6  & \textbf{0.116\%} &	\textbf{0.114\% }&	\textbf{0.113\%} &	\textbf{0.117\%} &	\textbf{0.126\%} \\
%BCH\_7  & \textbf{0.137\%} &	\textbf{0.134\%} &	\textbf{0.134\%} &	\textbf{0.138\%} &	\textbf{0.148\%} \\
%  \hline
%\end{tabular}
%\vspace{-8pt}
%\end{table}
%
\subsubsection{Energy Evaluation}
The overheads of read energy are shown in Figure~\ref{fig:R_E}.
Similarly, the read energy overhead is much more harmful to the normalized read energy of cross-point array, which is due to the fact that its based line read energy is quite small compared to the MOS based array. However, meanwhile, the improvement of write energy can be as much as 50\% for the cross-point array, compared to only 10\% improvement to the MOS based array. Besides, different from the write performances, the write energy for strong ECC, such as BCH\_8 or BCH\_16, will increase for large N, meaning a optimized subblock scheme is existing.
\begin{figure}
\centering
   \includegraphics[width=0.5\textwidth]{./figures/R_E.pdf}\\
  \vspace{-3pt}
  \caption{Read Energy Overhead (Based Line Energy = 4731 pJ for MOS based memory and 35.12 pJ for cross-point memory).}\label{fig:R_E}
  \vspace{0pt}
\end{figure}
\begin{figure}
\centering
   \includegraphics[width=0.5\textwidth]{./figures/W_E.pdf}\\
  \vspace{-5pt}
  \caption{Write Energy Improvement Read Energy Overhead (Based Line Energy = 105 nJ for MOS based memory and 4.85 nJ for cross-point memory.}\label{fig:W_E}
  \vspace{-12pt}
\end{figure}
%
%\begin{table}[!htb]
%\scriptsize \centering \caption{Read Energy overhead ratio of 128MB
%ECC-memristor based memory(Baseline Read
%Energy=4672pJ)}\label{tab:oh_read_E}
%\begin{tabular}{c|c|c|c|c|c}
%
%  \hline  \hline
%    N & 1 & 2 & 4 & 8 & 16\\
%    \hline
%SEC-DED & 				1.26	\% &					 2.20	\% &					 3.74	\% &					 6.30	\% &					10.46\% \\
%BCH\_2  & 				2.27	\% &					 3.90	\% &					 6.60	\% &					11.05	\% &					18.20\% \\
%BCH\_3  & 				3.33	\% &					 5.71	\% &					 9.70	\% &					16.26	\% &	\textbf{26.93\%} \\
%BCH\_4  &					4.37	\% &					 7.56	\% &	 \textbf{12.78\%} &	\textbf{21.51\%} &	\textbf{35.71\%} \\
%BCH\_5  & 				5.44	\% &  \textbf{ 9.37\%} &	 \textbf{15.90\%} &	\textbf{26.76\%} &	\textbf{44.60\%} \\
%BCH\_6  & \textbf{6.47\%} &	  \textbf{11.19\% }&	\textbf{18.99\%} &	 \textbf{32.03\%} &	\textbf{53.54\%} \\
%%BCH\_7  & \textbf{7.54\%} &	  \textbf{13.01\%} &	\textbf{22.12\%} &	 \textbf{37.35\%} &	\textbf{62.55\%} \\
%
%  \hline
%\end{tabular}
%\vspace{-8pt}
%\end{table}

%\subsubsection{Discussion on different memory size}
%Then the memory size is changed from 32MB to 256MB to evaluate the
%different impact of process variation. In order to simply demonstrate the
%trend, we choose the only one ECC code for each $N$. The ECC code chosen
%for each $N$ is the minimum requirement ECC for $p_E=10^{-4}$ and can be
%found in Table.\ref{tab:requir}. The area and energy over head are shown
%in Figure.\ref{fig:overhead}. Actually, the energy also has similar trend
%as these figures. It can be seen that, with the increase of memory size,
%the overhead ratio for area and latency will reduce in some sort. However,
%this kind of ratio reduction is not significant and has some exceptions at
%certain configurations with large $N$ .
%
%%\subsubsection{Discussion on spintronic memristor}
%%The spintronic memristor based ReRAM is also simulated in our work. Due to
%%the page limit, we only some most important observations as follow:
%%\begin{enumerate}
%%  \item Different from the thin film memristor, the spintronic
%%      memristor does not has a large resistance distinguishability,
%%      meaning that it is not suitable for the cross point array
%%      structure. Therefore, a MOSFET should be applied as the access
%%      device of the memristor cell.
%%  \item Since the access device is MOSFET, which is larger that the
%%      size of spintronic memristor, the area overhead will be more
%%      sensitive to the extra parity bits for ECC codes.
%%  \item From the simulation results we found that the impact of
%%      variation on a single spintronic memristor cell is much larger
%%      that thin film memristor. The Monte-Carlo simulation results
%%      show that under the constraint of $p_E=10^{-4}$, the write
%%      energy for spintronic memristor cell should be increased by
%%      about 25\%, compared to 15\% for thin film memristor.
%%  \item Also, by using the MOSFET as the access device, the two steps
%%      write operation is not necessary and therefore the write latency
%%      for memristor cell can be potentially reduced (assuming the
%%      spintronic memristor and thin film memristor have comparable
%%      write latency). Therefore, the energy and write latency overhead
%%      from the ECC have more impact on the spintronic memristor
%%      memory.
%%\end{enumerate}
%%Thus, we can conclude that the spintronic memristor is the spintronic is
%%more vulnerable to process variation.
%%\begin{figure}
%%\centering
%%  % Requires \usepackage{graphicx}
%%  \includegraphics[width=0.47\textwidth]{./figures/overhead.pdf}\\
%%  \vspace{-10pt}
%%  \caption{Area and latency overhead with different memory size}\label{fig:overhead}
%%  \vspace{-15pt}
%%\end{figure}
%%\subsubsection{Tradeoff among energy/latency/area}
%%Based on the results, we can get the guideline for designing a memristor
%%based ReRAM:
%%\begin{enumerate}
%%  \item For area and energy constrained design, the subblock size
%%      should be large enough and the simple ECC is helpful.
%%  \item For delay constrain design, the write delay is not a crucial
%%      issue and the read latency should be carefully consider since
%%      the overhead may be as large as 200\%. The read latency can
%%      benefit from smaller subblock size as well as simple ECC.
%%  \item The overhead ratio can also be reduced by increasing the size
%%      of the memristor based ReRAM.
%%      \item Spintronic memristor is more vulnerable to process
%%          variation.
%%\end{enumerate}
